Compiler Design 2

Outline s Refreshing unexpurgated Groundbreaking . The Dr. Wangs original lecture s s s s s tutorial of objective Compiler s s Introduction Setting Up the tutorial Graphical larboard The Alarm Clock objective Setting Design Environment Setting Design Constraints Overview of optimization Phases digest of Report DC tutorial 2 Introduction s s s Introduction s s s s The entailment Process Design Compiler Products Synthesis Programs and Tools Design Styles input signal and Output Formats User Interfaces Script institutionalises DC tutorial 4 The Synthesis ProcessStart revisal Verilog Code Read in Design Set Attributes Set Rea reheelic Timing Goal keep in line Design Errors No Yes Fix Bugs Change Constraints Modify Compile Attributes Ungroup Design Blocks The DC Products s DC Professional No multi-frequency clocking, latch-based m borrowing, pipeline re-timing, critical path resynthesis, in-place optimization, and incremental editing s DC Expert Include features for maxim izing performance s FPGA Compiler Targets only FPGA technology Optimize No Good? Yes Done DC tutorial 5 DC tutorial 6 1 Synthesis Tools HDL Design Analyzer HDL Compilers DesignWare DesignWare DeveloperArchitectural Optimization s s Architectural Optimization Gate-Level s s Design Analyzer Logic Optimization Design Compilers Cell program library Library Compiler s s Arithmetic Optimization Timing and Area-Based preference Sharing Sub-expression Removal Constraint-Driven Re blood Selection Inference of Synthetic Part (DesignWare) For more information HDL Compiler for Verilog fictitious character manual(a) Optimized Gate-level Netlist DC tutorial 7 DC Tutorial 8 DesignWare s DesignWare Developer Provide a library of high-level design components Adders, Multiplier, and so forth s sThe HDL compiler will select the priggish components for you based on your timing and subject field goals See Documentation Collection (open collection) Synopsys DesignWare 1997. 01 s constrain DesignWare Libraries DC Tutorial 9 DC Tutorial 10 DC Products s Cell Library s Library of basic cells used by DC AND, OR, XOR, etc. s Optimize your design at the gate level Using selected cell libraries s For FPGA compiler, it may contain more complex cells Xilinx CLBs, IOBs, etc. DC Tutorial 11 DC Tutorial 12 2 Library Compiler Design Styles s Yes, you can create your own cell libraries s s Hierarchical or shake off Com stash awayational or SequentialDC Tutorial 13 DC Tutorial 14 stimulus Formats s s s s Output Formats s s s s s VHDL Verilog PLA & EDIF 2. 00 Xilinx XNF s Synopsys binary format (. db files) VHDL Verilog EDIF 2. 00 Equation, LSI Logic, Mentor Graphics, PLA, state table, Tegas formats Xilinx XNF format DC Tutorial 15 DC Tutorial 16 User Interfaces s Scripts s shell dc_shell unix-like command shell dc_shell quit dc_shell cd my_dir dc_shell alias wv write -f verilog dc_shell pwd dc_shell history n dc_shell list -command dc_shell man dc_shell sh lpr s s s s shell design_analyzer graphical interface DC Tutorial 17 A position of command can be put together into a file called script Then, you dont need to re-type some the commands once more and again when using the dc_shell Scripts for this tutorial will be provided for your reference You can run them when you are sign without the X-window capability DC Tutorial 18 3 Locate Documentation s s s s s s s shell design_analyzer & select Help On-Line Documentation . Ignore the agora window with Titles select Cancel to close it focus on the one with File, Edit, take hold of select File Open Collection select Synopsys Synthesis Tools 1997. 1 and then click OK select Documents Formatted for effect and then click Open In the File, Edit, observe window, now you can select a list of on-line documents DC Tutorial 19 Setting Up the Tutorial Setting Up the Tutorial s s s s Creating The Directories s cp -r /baby/synopsys/doc/syn/tutorial . Home Directory tutorial Creating the dir ectories Setting paths and aliases Creating a start-up file Running tutorial with scripts db/ verilog/ vhdl/ appendix_A/ Script files work (empty) DC Tutorial 21 DC Tutorial 22 Path s s .synopsys_dc. frame-up file % source /usr/local/bin/setup. synopsys Or you can put it in . cshrc file % source . cshrc % rehash s s You can take a look of the setup file % more /usr/local/bin/setup. synopsys s Creating a . synopsys_dc. setup file can overwrite system default settings % cp /tutorial/. sysnopsys_dc. setup /. synopsys_dc. setup % vi /. synopsys_dc. setup company = Motorola Somerset designer = CEO view_ screeningground = while s It essentially setup the right environmental variables for you DC Tutorial 23 DC Tutorial 24 4More about setup file s Scripts s s % more . synopsys_dc. setup search_path = + search_path link_library target_library symbol_library define_design_lib s s s s s search_path = a directory + search_path if you cp tutorial into a directory other than h ome link_library stance of subdesgins referenced by the design target_library identify technology libraries symbol_library identify symbols library for generating/viewing courtlys define_design_lib identify a temporary place to store intermediate files created by the analyzer DC Tutorial 25 No X-Window, No Problem Find script files in /tutorial/appendix_A/. See Design Analyzer Reference manual of arms for more detail DC Tutorial 26 Graphical Interface s s Start % design_analyzer & Quit Select File Quit Menu Bar Graphical Interface beguile pushs Level Buttons Scroll Bar Message Area (view_background = while) View Window DC Tutorial 28 Mouse Buttons s Check Default Setup s Setup Defaults Left Button Select design and design objects s Mid Button Add or remove objects from a group of objects al asky selected s Right Button Bring up the pop-up fare DC Tutorial 29 DC Tutorial 30 5 Read in a Design s proceed a Design s File analyze & elaborate read File Save or Save As Once a design is selected s analyze read in VHDL/Verilog buffalo chip for syntax and synthesizale logic store as intermediate formats Use to read each sub-design + excrete level design s elaborate create the design from intermediate formats determine the correct coach-and-four size Use for top level design + sub-design with parameters passing in s read read design formats other than HDL (db, PLA, tc. ) DC Tutorial 31 DC Tutorial 32 A Design Has 4 Views s s s s s Design View s Design View Symbol View Schematic View Hierarchy View T View (No Use) After read in all 13 verilog files in the tutorial directory you first enter the Design View DC Tutorial 33 DC Tutorial 34 Symbol View s Schematic View s Select TIME_STATE_MACHINE and double-click on it - you enter the symbol view of the design crack on the schematic view button on the left hand side DC Tutorial 35 DC Tutorial 36 6 Hierarchy View s Design View Icons s s s s cad the up arrow (left hand side) to go back to des ign view doubleclick on put across Select View Change View Hierarchy TOP contains 6 modules Netlist read in as a netlist and optimized to gates Equation In VHDL, Verilog, or equivalence format that is partially or completely behavioral PLA Specified in PLA format State get across Specified in state table format Y=A+B 010-0 1-101 PLA State dodge Netlist Equation DC Tutorial 37 DC Tutorial 38 Command Window s dc_shell Commands Setup Command Window s For more information, see Design Compiler Reference manual of arms Fundamentals DC Tutorial 39DC Tutorial 40 Design Attributes s operating(a) Environment Sub-menu s Attributes are values you set to control the optimization process Select Attributes from the menu s The Attributes menu provide access to Set input and output remains Set drive strengths set loads Characterize subdesigns Select operating conditions Choose a wire load model Create or modify a clock DC Tutorial 41 Set design properties that describes the knowledgeable conditions of a design and the designs interaction with its surrounding drive strength on ports the time that signals arrive on ports load driven by output portsDC Tutorial 42 7 Optimization Constraints s Design Optimization s Set the goal for design optimization largest delay allowed greatest area allowed Select Tools Design Optimization See Design Compiler Reference Manual Optimization and Timing Analysis for more detail s Two set-constraint windows Design Constraints window Goals for area and power Design rules implied by technology library Test-related constraints (testability) Timing Constraints window Timing constraints s DC Tutorial 43 DC Tutorial 44Locating Problems s Generate Report s Before and after optimization, use Schematic View and Check Design to locate problems Generate schematic view Select Analysis Check Design Jump to a design object get hold of on an error or warning message in the Design error window Click on the show button Analysis Report DC Tutorial 45 DC Tutorial 46 Run a Script File s Setup Execute Script check out /tutorial/appendix_A/*. script dc_shell include The Alarm Clock Design DC Tutorial 47 8